1. Field of Use
This invention relates to semiconductor memories and more particularly to partially defective random access memories (RAMs).
2. Prior Art
For a number of years, different techniques have been employed which use memories with known defects. Early techniques involved the use of content addressable memories for locating the locations containing bad bits within the memory and enabling its replacement with good locations from another memory.
To reduce cost and speed up memory operations, one scheme disclosed in U.S. Pat. No. 3,434,116 circumvented bad memory cells of a bulk memory using replacement and read only memories having very small storage. The arrangement divided the word lines of the bulk memory into a large number of subword cell groups and substituting alternate subgroups in a replacement memory.
With advances in memory technology, techniques have been implemented that use memory components with known defects in the manufacture of memory systems. One technique involved the use of partially good memory chips/components in which at least three quarters of the memory array is known to be good. In this case, four different types of partially good chips are mixed with each type having one of its four quadrants containing defects. This technique is described in the article "The Case For Using Partially-Good Memory Devices" By Robert H. F. Lloyd, published in the April, 1977 issue of Computer Design.
Other techniques have employed partially good chips in which at least one-half of the memory array is known to be good. In this case, the memory system has to mix the appropriate amount of devices having good left and right halves to make a good working memory.
In order to produce partially good memory components with very high percentages of good cells, recently bulk devices containing at least two manufacturing defects in the array area have been proposed for use by one semiconductor manufacturer. The devices are of two types. A first type (type R) can contain up to a predetermined small number (e.g. 4,8) randomly distributed defective rows. The second type (type C) can contain up to the same predetermined number of defective columns and/or cells. Using this criteria of bulk device, a 64K memory component can contain 98 percent good cells.
The above criteria makes it possible to reduce the amount of additional storage for providing a good memory. The row or column defects within such memory components are random. Normally, in the failures in the row dimension are caused by metal opens resulting in less than a row being defective or by metal shorts resulting in two adjacent rows being shorted together. Therefore, in the case of two metal shorts/defects, there would be a loss of two rows per short or a total of four defective rows in a device. The majority of column failures result from an imbalance in the sense amplifier. This removes one column or results in one defective column. In the column dimension, there can be up to four defective sense amplifiers. A third type of defect that affects a bit could be dirt, a lattice defect or a mask defect. This type of failure could produce anywhere from one to four bit clusters, not necessarily near one another.
The article "Partial RAMs can fill today's memory boards" by Jerry Donaldson published in the Jan. 17, 1980 issue of Electronics describes a memory constructed from these types of partially good memory components. In the memory described, bit remapping hardware is employed and in operation when an address is given to the memory board, board logic included therein compares to those in a lookup table. When the address is there, an extra RAM is enabled. Data is written into or read from a row or column in the extra RAM corresponding to the address of a failing row or column in the partial bulk memory.
Another proposed scheme which utilizes bit mapping hardware requires that only double bit errors be remapped and that error detection and correction logic circuits included within the memory be used to correct single bit errors.
It has been found that the above schemes require a considerable amount of support logic circuits, such as bit remapping hardware. The result is that it becomes difficult and uneconomical to use a memory constructed from partially good chips within a conventional memory controller system. Also, such schemes as well as those previously discussed introduce delays in accessing data because of the need to perform comparison or replacement operations which lengthen memory cycle time. This in turn results in reduced memory performance.
A further disadvantage relates to decreases in fault tolerance produced by alpha particles or soft errors which can create double errors from single error faults.
Accordingly, it is a primary object of the present invention to provide a memory system constructed from partially good memory components which have few numbers of random defective rows or columns which has a minimum amount of support logic circuits.
It is a further object of the present invention to provide a memory controller system constructed from partially good memory components which minimizes memory access time and has high reliability.